OpenCPI Development Accelerator

Tender description

Summary of the work Development of OpenCPI components for FPGA and CPU based platforms. The task will involve writing C and VHDL based components as defined by the open source OpenCPI Git Lab with the associated defined documentation set. Expected Contract Length 5 months. Latest start date Monday 26 October 2020 Budget Range £600K for both DISCOVERY and ALPHA phases, to be run as Capped Time and Materials. Why the Work is Being Done The UK Ministry of Defence continues to research new and novel technologies. OpenCPI is a new software framework that is growing in popularity among the signal processing community. Dstl is keen to develop a tool to further the understanding through experimentation to establish how OpenCPI can be leveraged to support military technologies and communications. Dstl found that the range of components available within the framework was limiting. It was recognised that in order to fully understand the possibilities of OpenCPI, a larger range of components would be needed to support application development. Problem to Be Solved To establish a team able to produce an FPGA and CPU implementation of specific list of Digital Signal Processing elements to support experimentation. The components to be made are mathematical functions commonly found in other digital signal processing applications; from basic adders to Fast Fourier Transforms (FFT) in both C/C++ and VHDL/Verilog. The OpenCPI framework also provides testing of components and is completed using python wrappers. Who Are the Users As a user of the OpenCPI components. Dstl wants to be able to access a FPGA and CPU version of each mathematical function detailed in the backlog. Dstl wants to be able to immediately integrate the component with other elements which is possible because the components are built to the standards specified on the open source OpenCPI Git Lab. A standardised documentation set should be delivered with each component as per the guidance provided from the open source OpenCPI Git Lab. Early Market Engagement None. Work Already Done Dstl has conducted work on the OpenCPI framework and has experience in building components for OpenCPI. Existing Team The supplier will be working with a dedicated technical partner from Dstl for day to day interaction, alongside this there will be a small established team of FPGA and Software developers with Digital Signal Processing and Communications experience. Current Phase Not started Skills & Experience • Have previous experience with C / C++ and VHDL / Verilog. • Have working knowledge of scripting languages Python, Bash. • Have previous experience with Docker and Jira. Nice to Haves • Demonstrate with evidence the ability to deliver without authority funded capability enhancements (for example, procurement of additional ICT to support development activities). • Demonstrate with evidence the ability to conduct agile software development in-house, without support from subcontractors. • Demonstrate with evidence the ability to continue and evolve software development from a complex inherited codebase like opencpi. • Demonstrate with evidence experience developing and implementing software in C / C++ for embedded real time operating systems. • Demonstrate with evidence experience of developing and implementing VHDL / Verilog designs for real time signal processing applications. • Demonstrate with evidence experience of languages Python and Bash for scripting purposes. • Demonstrate with evidence experience and working knowledge of Docker and Jira. • Demonstrate with evidence the ability to produce appropriate levels of documentation, and conduct verification and validation of software. • Demonstrate with evidence experience using the Git Source Code Management (SCM) system and broader collaborative development tool suites. • Demonstrate with evidence of how you have provided customers with access to developmental and release versions of software source code, and engaged them in the development process. • Supplier must be able to work with a cyber risk level of “Very Low”. Reference: RAR-JG2R6F87 Please complete the Cyber Risk Assessment available at https://suppliercyberprotection.service.xgov.uk/. Work Location Dstl expects that the majority of the work to be conducted at the supplier own address, but there may be times when both formal meetings will take place at Dstl Working Arrangments The supplier shall utilise Agile development approach. This will allow development to closely align with requirements and assist evaluation throughout the project. The supplier shall host an initial kick-off meeting with the Technical-Partner and team. It's anticipated that the supplier will need more frequent interaction with Technical-partner during discovery phase. Dstl will assist in the configuration of a development environment. The supplier shall enable the remote development environment can be accessed by the technical-partner at OFFICIAL. Dstl will provide an initial 1 week of training(not necessarily consecutive days). Dstl requires the supplier to attend a face-to-face check in monthly(or teleconference). Security Clearance Must be able to handle OFFICIAL material only and pass Dstl's Research Worker process. Additional T&Cs DEFCON 76(EDN 12/06), DEFCON 501 (EDN0 05/07) - NOTE ONLY TO BE USED WHEN INTERPRETING THE DEFCONS); DEFCON 531 (EDN 11/14); DEFCON 608 (EDN 10/14); DEFCON 611 (EDN 02/16). FULL TEXT VERSIONS OF THE DEFCONS CAN BE FOUND ON THE AQUISSITION SYSTEM GUIDANCE ( ASG): HTTPS://WWW.GOV.UK/ACQUISTION-OPERATING-FRAMEWORK. DEFCON 658 (EDN 10/17). No. of Suppliers to Evaluate 10 Proposal Criteria • Demonstrate with evidence ability to follow industry best practice when conducting Verification and Validation (for example TickITplus). • Demonstrate with evidence experience of developing and implementing C/C++ embedded software applications. • Demonstrate with evidence experience of developing and implementing VHDL/Verilog firmware designs using FPGA development tools (Xilinx, Altera). • Demonstrate with evidence experience of developing and implementing software applications and firmware designs using modern digital signal processing techniques for radio communications. • Demonstrate with evidence examples of using the opencpi framework • Demonstrate with evidence experience developing software in the cyber operations domain in support of high threat and government organisations. • Provide a breakdown of the team structure (please include CVs of the team members doing the work). • Demonstrate experience of developing robust, high quality software solutions in demanding timeframes, within the quoted budget. • Provide estimated timeframes for the work (include Gantt chart with approximate sprint timeframes). • Describe how your Proposal will optimise costs and generate savings. • Detail and explain identified risks and dependencies. Provide details of offered approaches to manage these risks (include a Risk Register). Cultural Fit Criteria • Demonstrate consistent cultural commitment to agile software development practices. • Demonstrate with evidence that they are able to respond to an evolving customer requirement. • Demonstrate with evidence of sharing knowledge and experience with other team members. • Demonstrate with evidence being transparent and collaborative when making decisions. • Demonstrate with evidence an ability tosucessfully deliver within the UK Defence landscape • Provide a summary of the suppliers work ethos and working environment. Payment Approach Capped time and materials Evaluation Weighting Technical competence 70% Cultural fit 10% Price 20% Questions from Suppliers 1. To enable an estimated of the timescale for the work can you provide further detail on what sort of components and numbers you want to develop in the OpenCPI framework?Are the DISCOVERY and ALPHA phases both included in the 5 months? The component backlog is to be progressed through in an agile manner with Dstl technical partner and the "contractor" estimating the number of components that will be worked on in any given sprint based on the complexity of the selected components. There is no fixed number of components expected to be completed within the 5 month period, the backlog is not expected to be fully completed. 2. Are the DISCOVERY and ALPHA phases both included in the 5 months? Yes they are.